Electronic Design

Understand, Measure, And Optimize Clock Distribution Additive Jitter To Achieve Best Performance

High-speed communications require system designers to optimize clocking performance while adhering to both performance and cost-budget requirements. When selecting an optimal clock, the developer must ...
EDN

Comparing clock buffer data sheet specs for additive jitter

A clock distribution IC does not independently generate a clock signal; as such, phase noise cannot be measured unless an input is applied. The term most commonly used to quantify the quality of a ...
EDN

Buffers minimize jitter in clock distribution, differential signal lines

High performance clock buffers – those without phase-locked loops (PLLs) – are often used in communications designs for duplication, distribution and fanout of clock signals. Sensitivity to long-term ...
Embedded

Optimizing clock tree distribution in SoCs with multiple clock sinks

Tooptimize insertion delay and skew performance of the LUCT, it isimportant to note that the LUCT is allowed to feed through blockswhenever it is possible and beneficial to do so. Feed-through can ...
Hackaday

clock distribution

[Oleg Kutkov] decided to build a wideband SDR – for satellite communication research and monitoring, you know, the usual. He decided on a battery of HackRF boards – entire eight of them, in fact. Two ...
Electronic Design

High Performance Clock Distribution Solutions

ON Semiconductor has released two new clock distribution ICs. The NB6L56 presents the industry with a more advanced 2:1 signal management solution. Operating from a supply voltage of 2.5V and 3.3V, ...